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1 ? fn6469.1 isl54048, isl54049 ultra low on-resistance, +1.65v to +4.5v, single supply, dual spst analog switch the intersil isl54048 and isl54049 devices are low on-resistance, low voltage, bidirectional, dual single- pole/single-throw (spst) analog switches designed to operate from a single +1.65v to +4.5v supply. targeted applications include battery powered equipment that benefit from low r on (0.29 ) and fast switching speeds (t on = 40ns, toff = 20ns). the digital logic input is 1.8v logic-compatible when using a single +3v supply. cell phones, for example, often face asic functionality limitations. the number of analog input or gpio pins may be limited and digital geometries are not well suited to analog switch performance. this part may be used to ?mux-in? additional functionality while reducing asic design risk. the isl54048 and isl54049 are offered in a small form factor package, alleviating board space limitations. the isl54048 has two normally open (no) spst switches and the isl54049 has two normally closed (nc) spst switches. features ? on-resistance (r on ) - v+ = +4.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29 - v+ = +3.0v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33 - v+ = +1.8v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55 ?r on matching between channels . . . . . . . . . . . . . . . . . 0.06 ?r on flatness across signal range . . . . . . . . . . . . . . . . 0.03 ? single supply operation . . . . . . . . . . . . . . . +1.65v to +4.5v ? low power consumption (p d ). . . . . . . . . . . . . . . <0.45 w ? fast switching action (v+ = +4.3v) -t on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns -t off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns ? esd hbm rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kv ? 1.8v logic compatible (+3v supply) ? low icc current when vinh is not at the v+ rail ? available in 10 ld 1.8mmx1.4mmx0.5mm tqfn ? pb-free plus anneal available (rohs compliant) applications ? battery powered, handheld, and portable equipment - cellular/mobile phones - pagers - laptops, notebooks, palmtops ? portable test and measurement ? medical equipment ? audio and video switching related literature ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)? ? application note an557 ?recommended test procedures for analog switches? table 1. features at a glance isl54048, isl54049 number of switches 2 sw spst 4.3v r on 0.29 4.3v t on /t off 40ns/20ns 3v r on 0.33 3v t on /t off 50ns/27ns 1.8v r on 0.55 1.8v t on /t off 70ns/54ns package 10 ld 1.8mmx1.4mmx0.5mm tqfn ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # isl54048iruz-t b -40 to +85 10 ld 1.8x1.4x0.5 tqfn (0.40mm pitch) tape and reel l10.1.8x1.4a isl54049iruz-t c -40 to +85 10 ld 1.8x1.4x0.5 tqfn (0.40mm pitch) tape and reel l10.1.8x1.4a note: intersil pb-free plus anneal products employ special pb-free material sets ; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible wi th both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet june 11, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6469.1 june 11, 2007 pinouts (note 1) isl54048 (10 ld tqfn) top view isl54049 (10 ld tqfn) top view note: 1. switches shown for logic ?0? input. v+ no1 com1 in1 n.c. no2 com2 in2 n.c. gnd 1 2 3 4 5 10 9 8 7 6 v+ n.c. com1 in1 nc1 n.c. com2 in2 nc2 gnd 1 2 3 4 5 10 9 8 7 6 truth table logic isl54048 isl54049 0offon 1onoff note: logic ?0? 0.5v. logic ?1? 1.4v with a 3v supply. pin descriptions pin function v+ system power supply input (+1.65v to +4.5v) gnd ground connection in digital control input com analog switch common pin nox analog switch normally open pin ncx analog switch normally closed pin nc no connect isl54048, isl54049
3 fn6469.1 june 11, 2007 absolute maximum rati ngs thermal information v+ to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5v input voltages no, nc, in (note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) output voltages com (note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((v+) + 0.5v) continuous current no, nc, or com . . . . . . . . . . . . . . . . . 300ma peak current no, nc, or com (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . . . . . . . . . . 500ma esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kv operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance (typical) ja (c/w) 10 ld tqfn package (note 3) . . . . . . . . . . . . . . . 143 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. extended operation above the recommended operating conditions could result in decre ased reliability. the absolute maximum ratings are stress only ratings and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 2. signals on nc, no, in, or com exceeding v+ or gnd are clamped by internal diodes. limi t forward diode current to maximum curr ent ratings. 3. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications - 3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v inh = 1.6v, v inl = 0.5v (notes 4, 8), unless otherwise specified. parameter test conditions temp (c) min (note 5) typ max (note 5) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 3.9v, i com = 100ma, v no or v nc = 0v to v+, (see figure 4) 25 - 0.30 - full - 0.35 - r on matching between channels, r on v+ = 3.9v, i com = 100ma, v no or v nc = voltage at max r on, (note 8) 25 - 0.06 - full - 0.08 - r on flatness, r flat(on) v+ = 3.9v, i com = 100ma, v no or v nc = 0v to v+, (note 6) 25 - 0.03 - full - 0.04 - no or nc off leakage current, i no(off) or i nc(off) v+ = 4.5v, v com = 0.3v, 3v, v no or v nc = 3v, 0.3v 25 -100 - 100 na full -195 - 195 na com on leakage current, i com(on) v+ = 4.5v, v com = 0.3v, 3v, or v no or v nc = 0.3v, 3v, or floating 25 -100 - 100 na full -195 - 195 na dynamic characteristics turn-on time, t on v+ = 3.9v, v no or v nc = 3.0v, r l = 50 , c l = 35pf, (see figure 1) 25 - 40 - ns full - 50 - ns turn-off time, t off v+ = 3.9v, v no or v nc = 3.0v, r l = 50 , c l = 35pf, (see figure 1) 25 - 20 - ns full - 30 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , see figure 2 25 - 170 - pc off isolation r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms , (see figure 3) 25 - 62 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms , (see figure 5) 25 - -85 - db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 - 0.005 - % isl54048, isl54049
4 fn6469.1 june 11, 2007 no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v, (see figure 6) 25 - 62 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v, (see figure 6) 25 - 176 - pf power supply characteristics power supply range full 1.65 4.5 v positive supply current, i+ v+ = +4.5v, v in = 0v or v+ 25 - - 0.1 a full - - 1 a positive supply current, i+ v+ = +4.2v, v in = 2.85v 25 - - 12 a digital input characteristics input voltage low, v inl full - - 0.5 v input voltage high, v inh full 1.6 - - v input current, i inh , i inl v+ = 4.5v, v in = 0v or v+ full -0.5 - 0.5 a electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (notes 4, 8), unless otherwise specified. parameter test conditions temp (c) min (note 5) typ max (note 5) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (see figure 4) 25 - 0.35 0.5 full - - 0.7 r on matching between channels, r on v+ = 2.7v, i com = 100ma, v no or v nc = voltage at max r on , (note 7) 25 - 0.06 0.07 full - - 0.08 r on flatness, r flat(on) v+ = 2.7v, i com = 100ma, v no or v nc = 0v to v+, (note 6) 25 - 0.03 0.15 full - - 0.15 no or nc off leakage current, i no(off) or i nc(off) v+ = 3.3v, v com = 0.3v, 3v, v no or v nc = 3v, 0.3v 25 - 0.9 - na full - 30 - na com on leakage current, i com(on) v + = 3.3v, v com = 0.3v, 3v, or v no or v nc = 0.3v, 3v, or floating 25 - 0.8 - na full - 30 - na dynamic characteristics turn-on time, t on v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf, (see figure 1) 25 - 50 - ns full - 60 - ns turn-off time, t off v+ = 2.7v, v no or v nc = 1.5v, r l = 50 , c l = 35pf, (see figure 1) 25 - 27 - ns full - 35 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , ( see figure 2) 25 - 94 - pc off isolation r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms , (see figure 3) 25 - 62 - db crosstalk (channel-to-channel) r l = 50 , c l = 5pf, f = 100khz, v com = 1v rms , (see figure 5) 25 - -85 - db total harmonic distortion f = 20hz to 20khz, v com = 2v p-p , r l = 600 25 - 0.005 - % no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v, (see figure 6) 25 - 65 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v, (see figure 6) 25 - 181 - pf electrical specifications - 3v supply test conditions: v+ = +3.9v to +4.5v, gnd = 0v, v inh = 1.6v, v inl = 0.5v (notes 4, 8), unless otherwise specified. (continued) parameter test conditions temp (c) min (note 5) typ max (note 5) units isl54048, isl54049
5 fn6469.1 june 11, 2007 power supply characteristics positive supply current, i+ v+ = +3.6v, v in = 0v or v+ 25 - 0.01 - a full - 0.52 - a digital input characteristics input voltage low, v inl 25 - - 0.5 v input voltage high, v inh 25 1.4 - - v input current, i inh , i inl v+ = 3.3v, v in = 0v or v+ full -0.5 - 0.5 a electrical specifications - 1.8v supply test conditions: v+ = +1.65v to +2v, gnd = 0v, v inh = 1.0v, v inl = 0.4v (notes 4, 8), unless otherwise specified. parameter test conditions temp (c) min (note 5) typ max (note 5) units analog switch characteristics analog signal range, v analog full 0 - v+ v on-resistance, r on v+ = 1.65v, i com = 100ma, v no or v nc = 0v to v+, (see figure 4) 25 - 0.7 0.8 full - - 0.85 dynamic characteristics turn-on time, t on v+ = 1.65v, v no or v nc = 1.0v, r l =50 , c l = 35pf, (see figure 1) 25 - 70 - ns full - 80 - ns turn-off time, t off v+ = 1.65v, v no or v nc = 1.0v, r l =50 , c l = 35pf, (see figure 1) 25 - 54 - ns full - 65 - ns charge injection, q c l = 1.0nf, v g = 0v, r g = 0 , ( see figure 2) 25 - 42 - pc no or nc off capacitance, c off f = 1mhz, v no or v nc = v com = 0v, (see figure 6) 25 - 70 - pf com on capacitance, c com(on) f = 1mhz, v no or v nc = v com = 0v, (see figure 6) 25 - 186 - pf digital input characteristics input voltage low, v inl 25 - - 0.4 v input voltage high, v inh 25 1.0 - - v input current, i inh , i inl v+ = 2.0v, v in = 0v or v+ full -0.5 - 0.5 a notes: 4. v in = input voltage to perform proper function. 5. the algebraic convention, whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. 6. flatness is defined as the di fference between maximum and minimum value of on- resistance over the specified analog signal ran ge. 7. r on matching between channels is calculated by s ubtracting the channel with the highest max r on value from the channel with lowest max r on value, between nx1 and nx2. 8. parts are 100% tested at +25c. limits across full temperature range are guaranteed by design and correlation. electrical specifications - 3v supply test conditions: v+ = +2.7v to +3.3v, gnd = 0v, v inh = 1.4v, v inl = 0.5v (notes 4, 8), unless otherwise specified. (continued) parameter test conditions temp (c) min (note 5) typ max (note 5) units isl54048, isl54049
6 fn6469.1 june 11, 2007 test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times figure 2a. measurement poin ts figure 2b. test circuit figure 2. charge injection figure 3. off isolation test circuit figure 4. r on test circuit 50% t r < 5ns t f < 5ns t off 90% v+ 0v v nx1 0v t on logic input switch input switch output 90% v out v out v (no or nc) r l r l r on () + ---------------------------- = switch input logic input v out r l c l com nx1 or nx2 in 50 35pf gnd v+ c v out v out on off on q = v out x c l switch output logic input v+ 0v c l v out r g v g gnd com nx1 or nx2 v+ c logic input in repeat test for all switches. analyzer r l signal generator v+ c 0v or v+ com in gnd signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. nx1 or nx2 v+ c 0v or v+ com in gnd v nx v 1 r on = v 1 /100ma 100ma repeat test for all switches. nx1 or nx2 isl54048, isl54049
7 fn6469.1 june 11, 2007 detailed description the isl54048 and isl54049 are bidirectional, dual single pole/single throw (spst ) analog switches that offer precise switching capability from a single 1.65v to 4.5v supply with low on-resistance (0.29 ) and high speed operation (t on = 40ns, t off = 20ns). the devices are especially well suited for portable battery powered equipment due to their low operating supply voltage (1.65v), low power consumption (4.5w max), low leakage currents (195na max) and the tiny tqfn package. the ultra low on-resistance and r on flatness provide very low insertion loss and distortion to applications that require signal reproduction. external v+ series resistor for improved esd and latch-up immunity, intersil recommends adding a 100 resistor in series with the v+ power supply pin of the ic (see figure 7). during an overvoltage transient event, such as occurs during system level iec 61000 esd test ing, substrate currents can be generated in the ic that can trigger parasitic scr structures to turn on, creating a low impedance path from the v+ power supply to ground. this will result in a significant amount of current flow in the ic which can potentially create a latch-up state or permanently damage the ic. the external v+ resistor limits the current during this over-stress situation and has been found to prevent latch-up or destructive damage for many overvoltage transient events. under normal operation the sub-microamp i dd current of the ic produces an insignificant voltage drop across the 100 series resistor resulting in no impact to switch operation or performance. supply sequencing and overvoltage protection with any cmos device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the ic. all i/o pins contain esd protection diodes from the pin to v+ and to gnd (see figure 8). to prevent forward biasing these diodes, v+ must be applied before any input signals, and the input signal voltages must remain between v+ and gnd. if these conditions cannot be guaranteed, then precautions must be implemented to prohib it the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. the following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the v+ rail. logic inputs can be protected by adding a 1k resistor in series with the logic input (see figure 8). the resistor limits the input current below the threshold that produces figure 5. crosstalk test circuit figure 6. capacitance test circuit test circuits and waveforms (continued) 0v or v+ analyzer v+ c signal generator r l gnd in 1 com 50 n.c. com signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. nx1 or nx2 nx1 or nx2 v+ c gnd com in impedance analyzer 0v or v+ repeat test for all switches. nx1 or nx2 figure 7. v+ series resistor for enhanced esd and latch-up immunity in comx 100 nx v+ gnd c optional protection resistor isl54048, isl54049
8 fn6469.1 june 11, 2007 permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. this method is not acceptable for the signal path inputs. adding a series resistor to the switch input defeats the purpose of using a low r on switch. connecting schottky diodes to the signal pins (as shown in figure 8) will shunt the fault current to the supply or to ground thereby protecting the switch. these schottky diodes mu st be sized to handle the expected fault current. power-supply considerations the isl54048 and isl54049 construction is typical of most single supply cmos analog switches, in that they have two supply pins: v+ and gnd. v+ and gnd drive the internal cmos switches and set their analog voltage limits. unlike switches with a 4v maximum supply voltage, the isl54048 and isl54049 5.5v maximum supply voltage provides plenty of room for the 10% tolerance of 4.3v supplies, as well as room for overshoot and noise spikes. the minimum recommended supply voltage is 1.65v. it is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. refer to ?electrical specifications? on page 3 and the typical performance curves on page 9 for details. v+ and gnd also power the internal logic and level shiftiers. the level shiftiers convert the input logic levels to switched v+ and gnd signals to drive the analog switch gate terminals. this family of switches c annot be operated with bipolar supplies because the input switching point becomes negative in this configuration. logic-level thresholds this switch family are 1.8v l ogic compatible (0.5v and 1.4v) over a supply range of 2.7v to 4.5v (see figure 18). at 2.7v, the v il level is about 0.53v. this is still above the 1.8v logic guaranteed low output maximum level of 0.5v, but noise margin is reduced. the digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. driving the digital input signals from gnd to v+ with a fast transition time minimizes power dissipation. the isl54048 and isl54049 have been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0v to v+). for example, driving the device with 2.85v logic (0v to 2.85v) while operating with a 4.2v supply the device draws only 12 a of current (see figure 16 for v in = 2.85v). frequency performance in 50 systems, the isl54048 and isl54049 have a -3db bandwidth of 120mhz (see figure 21). the frequency response is very consistent over a wide v+ range, and for varying analog signal levels. an off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch?s input to its output. off isolation is the resistance to this feedthrough, while crosstalk indicates the amount of feedthrough from one switch to another. figure 22 details the high off isolation and crosstalk rejection provided by this part. at 100khz, off isolation is about 62db in 50 systems, decreasing approx imately 20db per decade as frequency increases. higher load impedances decrease off isolation and crosstalk rejection due to the voltage divider action of the switch off impedance and the load impedance. leakage considerations reverse esd protection diodes are internally connected between each analog-signal pin and both v+ and gnd. one of these diodes conducts if any analog signal exceeds v+ or gnd. virtually all the analog leakage current comes from the esd diodes to v+ or gnd. although the esd diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. each is biased by either v+ or gnd and the analog signal. this means their leakages will vary as the signal varies. the difference in the two diode leakages to the v+ and gnd pins constitutes the analog- signal-path leakage current. all analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. this is why both sides of a given switch can show leakage curren ts of the same or opposite polarity. there is no connection between the analog signal paths and v+ or gnd. figure 8. overvoltage protection gnd v com v nx v+ in x optional protection resistor optional schottky diode optional schottky diode isl54048, isl54049
9 fn6469.1 june 11, 2007 typical performance curves t a = +25c, unless otherwise specified figure 9. on-resistance vs supply voltage vs switch voltage figure 10. on-resistance vs supply voltage vs switch voltage figure 11. on-resistance vs supply voltage vs switch voltage figure 12. on-resistance vs switch voltage figure 13. on-resistance vs switch voltag e figure 14. on-resistance vs switch voltage 012345 r on ( ) v com (v) i com = 100ma 0.25 0.26 0.27 0.28 0.29 0.30 v+ = 4.5v v+ = 4.3v v+ = 3.9v r on ( ) v com (v) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i com = 100ma 0.28 0.29 0.30 0.31 0.32 0.33 0.34 0.35 v+ = 3.3v v+ = 3v v+ = 2.7v 0 0.5 1.0 1.5 2.0 r on ( ) v com (v) i com = 100ma 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 v+ = 2v v+ = 1.65v v+ = 1.8v 012345 r on ( ) v com (v) v+ = 4.3v i com = 100ma +85c -40c +25c 0.20 0.25 0.30 0.35 0 0.51.01.52.02.53.03.5 r on ( ) v com (v) +85c -40c v+ = 3.3v i com = 100ma +25c 0.20 0.25 0.30 0.35 0.40 0 0.5 1.0 1.5 2.0 2.5 3.0 r on ( ) v com (v) +85c -40c v+ = 2.7v +25c i com = 100ma 0.25 0.30 0.35 0.40 isl54048, isl54049
10 fn6469.1 june 11, 2007 figure 15. on-resistance vs switch voltag e figure 16. supply current vs vlogic voltage figure 17. charge injection vs swit ch voltage figure 18. digital sw itching point vs supply voltage figure 19. turn-on time vs supply voltage fi gure 20. turn-off time vs supply voltage typical performance curves t a = +25c, unless otherwise specified (continued) 0 0.5 1.0 1.5 2.0 r on ( ) v com (v) +85c -40c v+ = 1.8v i com = 100ma +25c 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 i on (a) v in1 and v in2 (v) v+ = 4.2v 12345 0 50 100 150 200 sweeping both logic inputs q (pc) v com (v) 012345 -100 -50 0 50 100 150 200 v+ = 3v v+ = 1.8v v+ = 4.3v v+ (v) v inh and v inl (v) 1.52.02.53.03.54.04.5 v inh v inl 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 t on (ns) v+ (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 25 100 150 200 250 +85c -40c +25c t off (ns) v+ (v) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150 200 +85c -40c +25c isl54048, isl54049
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6469.1 june 11, 2007 die characteristics substrate potential (powered up): gnd transistor count: 114 process: submicron cmos figure 21. frequency response figur e 22. crosstalk and off isolation typical performance curves t a = +25c, unless otherwise specified (continued) frequency (hz) 0 -20 normalized gain (db) gain phase v+ = 3.0v 0 20 40 60 80 phase () 1m 10m 100m 300m v in = 0.2v p-p to 2v p-p r l = 50 frequency (hz) 1k 100k 1m 100m 500m 10k 10m -110 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 crosstalk (db) off isolation (db) 110 10 20 30 40 50 60 70 80 90 100 isolation crosstalk v+ = 4.3v isl54048, isl54049
12 fn6469.1 june 11, 2007 isl54048, isl54049 ultra thin quad flat no-lead plastic package (utqfn) 6 b e a d 0.10 c 2x c 0.05 c a 0.10 c a1 seating plane index area 2 1 n top view side view nx (b) section "c-c" e cc 5 c l terminal tip (a1) l 0.10 c 2x l1 e nx l bottom view 5 7 2 1 pin #1 id (datum a) (datum b) 0.10 m c a b 0.05 m c nx b 10x 5 0.50 0.20 0.40 1.80 0.40 0.20 2.20 1.00 0.60 1.00 land pattern 10 l10.1.8x1.4a 10 lead ultra thin quad flat no-lead plastic package symbol millimeters notes min nominal max a 0.45 0.50 0.55 - a1 - - 0.05 - a3 0.127 ref - b 0.15 0.20 0.25 5 d 1.75 1.80 1.85 - e 1.35 1.40 1.45 - e 0.40 bsc - l 0.35 0.40 0.45 - l1 0.45 0.50 0.55 - n102 nd 2 3 ne 3 3 0- 12 4 rev. 3 6/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on d and e side, respectively. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. maximum package warpage is 0.05mm. 8. maximum allowable burrs is 0.076mm in all directions. 9. jedec reference mo-255. 10. for additional information, to assist with the pcb land pattern design effort, see intersil technical brief tb389.

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